Assinging inout port to inout in both directions

Question

For simulation purposes, using Verilog, I would like to create a block that only has 2 inout ports (say left and right) and will be transmitting signals either from left to right or from right to left. It can be assumed that the block will be active only during the transition and will be waiting for inputs for the rest of the time. But I'm not allowed to use any other ports. So the module definition will be something like this in theory:

module blackbox(inout left, inout right)
  assign left = right;
  assign right = left;

  specify
    (left => (right:1'b1)) = 7;
    (right => (left:1'b1)) = 8;
  endspecify
endmodule

Is there a solution for this?

---

As a 2nd question, The problem can be simplified by determining the direction after the placement. For example, if the block placed in one location it will always transmit signal from left to right but in another location it can be from right to left. Would it be possible to somehow code this inside the module?

Thanks,

Answer 1

In Verilog

module blackbox(inout .left(internal), inout .right(internal));
 wire internal;
  specify
    (left => (right:1'b1)) = 7;
    (right => (left:1'b1)) = 8;
  endspecify
endmodule

or

 module blackbox(inout left, right);
     tran t(left,right); // some simulators might require this to work with specify block
      specify
        (left => (right:1'b1)) = 7;
        (right => (left:1'b1)) = 8;
      endspecify
    endmodule

In SystemVerilog:

 module blackbox(inout left, right)
   alias left = right;
      specify
        (left => (right:1'b1)) = 7;
        (right => (left:1'b1)) = 8;
      endspecify
 endmodule

For your second question, I'm not sure why you would need this for a simulation model, or how you would get placement information into the netlist.