Can we force value for user defined datatypes in simulator?

Question

Sorry, It may be very basic question. But I could not find any solution on and off the line. I am using vivado 2013.4 version for my tasks. Here is my code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
use IEEE.NUMERIC_STD.ALL;

package my_package is
    type my_datatype is 
    record 
        n1 : real ;
        n2 : unsigned(31 downto 0);
        n3 : unsigned(31 downto 0);
        n4 : unsigned(31 downto 0);
        nE : integer;
    end record;
end my_package;

use work.my_package.all;

entity read_mydata is
     Port (a_in : inout my_datatype ; b_out : out my_datatype );
end read_mydata;

architecture Behavioral of read_mydata is
begin
    b_out <= (abs(a_in.n1), a_in.n2, a_in.n3, a_in.n4, abs(a_in.nE));  
end Behavioral;

The code has no visible error. My question is, how to force the input in the simulator? I tried forcing the a_in using comma and semicolon seperators. There was error. For example, In Tcl console,

 add_force {/read_file/a_in} -radix bin {2.5, 5, 4, 3, -2 0ns}
 ERROR: [#UNDEF] Time value 5, is not a valid number

Is this program synthesisable?

Answer 1

According to the UG835 for Vivado 2013.4, your TCL command is not correct. You cannot assign all fields in the record at once. It seems that you changed the name of your package as well in the meantime because read_file is not mentioned in your original code. Anyway, you can run the following:

add_force {/read_mydata/a_in.n1} -radix dec {2.5 0ns}
add_force {/read_mydata/a_in.n2} -radix dec {5 0ns}
add_force {/read_mydata/a_in.n3} -radix dec {4 0ns}
add_force {/read_mydata/a_in.n4} -radix dec {3 0ns}
add_force {/read_mydata/a_in.nE} -radix dec {-2 0ns}

I tried your code in Vivado 2017.1. (I don't have 2013.4 at my disposal.) In my version, you can also right-click on the signal in the "Name" column and select "Force Constant..."