verilog output stuck on last if statement

Problem: I'm synthesizing my code, which reads 1200 16 bit binary vectors, analyzes them and sets a 2 bit register named classe depending on the behavior of 4 if statements. The problem seems to be that classe is stuck on the last if statement - where classe is set to bit 11, or 3.

My code worked fine in when I was using a testbench.

I'm thinking it is stuck because somehow the always block is reading all 1200 vectors at once, as seen in the simulation, instead of one every clock edge?

I've attached a simulation screenshot here: https://i.sstatic.net/bbo35.jpg

module final_final_code
(
output reg [ 0:1] classe

    );

reg [0:15] memory [0:1199];
reg[0:15] vect:
integer i; 

//// Internal Oscillator
defparam OSCH_inst.NOM_FREQ = "2.08";
OSCH OSCH_inst
    (
    .STDBY(1'b0),       // 0=Enabled, 1=Disabled also Disabled with Bandgap=OFF
    .OSC(osc_clk),
    .SEDSTDBY()             // this signal is not required if not using SED
    );

initial begin
$readmemb("C:/Users/KP/Desktop/data.txt", memory, 0, 1199);
i = 0;
end


  always  @(posedge osc_clk) begin
     vect = memory[i];
     if ((memory[i][3] == 1'b0)) begin
         classe = 2'b10;
     end

     if ((memory[i][11] == 1'b0)) begin
          classe = 2'b01;
    end

    if ((memory[i][8] == 1'b1 &&  memory[i][4] + memory[i][5] + memory[i][6] + memory[i][7] >= 4'b0100)) begin
        classe = 2'b00;
    end

    if ((memory[i][0] + memory[i][1] + memory[i][2] + memory[i][3] + memory[i][4] + memory[i][5] + memory[i][6] + memory[i][7] + memory[i][8] + memory[i][9] + memory[i][10] + memory[i][11] + memory[i][12] + memory[i][13] + memory[i][14] + memory[i][15] <= 1'b1)) begin
        classe = 2'b11;
end
     i = i + 1'd1;
     if (i == 4'd1199) begin
         i = 0;
    end
end





endmodule

Solution

Apart from what john_log says:

Your last if statement is always TRUE. You are adding 1-bit operands and comparing against a 1-bit result thus the results is 1'b1 or 1'b0 which is always <= 1'b1.

You should check if your FPGA tool supports this:

initial begin
$readmemb("C:/Users/KP/Desktop/data.txt", memory, 0, 1199);
i = 0;
end

Especially the loading of a memory from a file by the synthesis tool. It was not possible the last time I used an FPGA.