using divider core from xilinx

Question

I do not know how to properly use divisor ip core from xilinx and what i am doing wrong.

Here is code reduced to problem and all I do extra in ISE is that I add divisor core whit

CE - enabled
Quotient width 17
Divisor width 11
Remainder
Signed
2 clocks per devision

and ucf file whit NET "CLK_50MHZ" definition

I cant get rid of this error http://www.xilinx.com/support/answers/13873.htm

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_signed.ALL;


use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pg is
 Port ( CLK_50MHz : in  STD_LOGIC );
end pg;

architecture Behavioral of pg is

signal CLK : std_logic;
signal div_ce :  std_logic := '0' ;
signal div_rfd :  std_logic;
signal dividend_std : std_logic_vector (16 downto 0) := "00000000000000000";
signal divisor_std: std_logic_vector (10 downto 0) := "00000000000";
signal quotient_std:  std_logic_vector (16 downto 0) ;
signal fractional_std :  std_logic_vector (10 downto 0);


component divider is 
port (   clk: in  std_logic;
            rfd: in  std_logic;
            ce:  in std_logic;
            dividend : in std_logic_vector (16 downto 0);
            divisor: in  std_logic_vector (10 downto 0);
            quotient: out std_logic_vector (16 downto 0); 
            fractional : out  std_logic_vector (10 downto 0)
            );          
end component;


begin   
cdiv: process(CLK_50MHz)
begin
    if(CLK_50MHz'event and CLK_50MHz='1') then
        CLK<=not CLK;
    end if;
end process cdiv;


VVV:divider
port map( clk=>CLK,
         rfd=>div_rfd, 
         ce=>'1',
         dividend=>dividend_std,  
         divisor=>divisor_std,   
         quotient=>quotient_std,  
         fractional=>fractional_std
);

end Behavioral;

Answer 1

Not sure what your error message is, but here's some comments based on the code.

First:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_signed.ALL;


use IEEE.NUMERIC_STD.ALL;

You really don't want all those libraries, they'll collide in various ways.

Just use numeric_std (and in fact, you don't even need that for this example)

Second:

You might also suffer as your top level entity pg only has a clock input. The tools will notice that no outputs are ever sent to the outside world and optimise the whole thing away!

Try bringing the divider input and outputs to the outside world.