Assign 2d std_logic_vector with another 1d std_logic_vector in VHDL

Question

I have this port

PORT (
    A : IN  STD_LOGIC_VECTOR(31 downto 0);
    B : IN  STD_LOGIC_VECTOR(31 downto 0);
    C : IN  STD_LOGIC_VECTOR(31 downto 0);
    F : OUT STD_LOGIC_VECTOR(31 downto 0);
);

and this signal

SIGNAL data : std_logic_2d(31 downto 0, 2 downto 0);

I need to assign data(all,0) with A and data(all,1) with B and so on
like that

data(?,0) <= A;
data(?,1) <= B;
data(?,2) <= C;

what can I put instead of "?" in the code to perform it??

Answer 1

Solution 1 - process and for-loop:

A process is used to host a sequential for loop. You need to add all read signals to the sensitivity list: A, B, C.

process(A, B, C)
begin
  for i in A'range loop
    data(i, 0) <= A(i);
    data(i, 1) <= B(i);
    data(i, 2) <= C(i);
  end loop;
end process;

Solution 2 - for-generate:

A generate loop is used to create lots of concurrent assignments.

gen: for i in A'range generate
  data(i, 0) <= A(i);
  data(i, 1) <= B(i);
  data(i, 2) <= C(i);
end generate;

Solution 3 - a assignment procesdure:

A procedure is used to encapsulate the assignment to rows.

procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural) is
  variable temp : std_logic_vector(slm'range(1));
begin
  temp := slv;
    for i in temp'range loop
      slm(i, ColIndex)  <= temp(i);
  end loop;
end procedure;

Source: PoC.vectors.assign_col

Usage:

assign_col(data, A, 0);
assign_col(data, B, 1);
assign_col(data, C, 2);

The package PoC.vectors contains a lot of new types, functions and procedures to handle true std_logic based 2D arrays in VHDL.