How to add additional IO under certain condition to RoCCIO in Chisel

Question

I am trying to add custom instruction to RISC-V by using ROCC, and my base is the rocket-chip. Some of the accelerators requires additional IO to be added to the RoCCIO class. I am trying to understand the conditional instantiation of additional IO's, like in the case of the Floating point unit & page table walker (PTW) ,I am new to Chisel & Scala so it very cryptic to me.

Can someone explain how this code implement conditional instantiation:

    class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
       val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
       val fpu_req = Decoupled(new FPInput)
       val fpu_resp = Decoupled(new FPResult).flip
}

Answer 1

Your example of RoCC is using dead code elimination (however, you must be careful to tie off the signals you aren't using just to be sure).

You can instead use Option to perform conditional instantiation in your IO bundle declaration:

val a = if (cond) Some(UInt(width=5.W)) else None