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verilogvivado

Unused sequential logic element removed. Unsure why it is unused


The code runs without any syntax errors but when I try to port the code over to a basys board and use it it doesn't work. I think the given Vivado error is the problem but I am unsure. I don't know how distance shows up as unused. Vivado error (sorry I don't have enough reputation to put the picture directly)

`timescale 1us/1us
module ProximitySensor(output reg trigger, input echo, input clk, output reg isCrash);
integer distance;

always @(posedge clk) //every clock pulse
    begin
        case (echo)
        0:
            begin

                if(distance <= 294117 && distance > 0)
                    begin
                        isCrash <= 1;
                        distance <=0;
                    end
                 else if(distance > 294117)
                    begin
                        isCrash <= 0;
                        distance <= 0;
                    end
                    trigger = 1;

            end       
        1:
            begin
                trigger <= 0;
                distance <= distance + 1;
            end
            endcase
    end

endmodule


Solution

  • open Synthesis->Schematic and look for the distance registers (distance_reg[..]). Check if really all your registers are removed. I just ran your design I also get the message but most of them are still present. (At least uptil register 27).

    If they are really all gone the most likely cause is that the 'echo 'signal is always 0.

    Next: It is bad style to use an integer as register. The normal coding style is to use:

    reg [31:0] distance;
    

    (Also integer is signed and you probably want an unsigned counter)

    Last: your "trigger = 1;" code:

    1. It should be non-blocking: "trigger <= 1;" (Although I prefer 1'b1)
    2. The indent is wrong. It suggests it belongs to the "if(distance > 294117)" section but it does not.