Flushing data cache (dcbf assembly instruction)

Question

Context:

I currently want to flush my L1 DATA cache (target: NXP P2020 Qoriq e500).

I have an issue while using "dcbf" instruction:

dcbf r3, r4 // with r3 and r4 defining the address of the DATA cache

Issue:
My problem is that I don't know what parameter to give to this instruction to reach the DATA cache and flush the line ?

I tried with a "just created" variable :

int i = 0; 
// let assume r3 = &i
dcbf 0, r3
isync
msync

I thougth that the dcbf instruction will reach the data cache via &i parameter, but when I futher look into the memory via a probe, I see the cache as not flushed and not invalidated.

Answer 1

Well,

I finally did this to replace my L1 data cache entries:

FlushL1DCache:
flushloop:
    lwz     r5, 0(r3)       /* Load data to L1 data cache to replace current entries */
    addi    r3, r3, 0x20    /* adds 32 bytes to r3 */
    cmpw    r3, r4          /* if r3 == r4  -> exit the loop */
    ble     flushloop
    msync
    isync
    blr

This code replace L1 data cache entries by dummy ones before invalidation.