33 * 33 bit using 16 bit DSPs

Question

I want to write a vhdl/verilog code to multiply 2 33 vector using 16 bit dsps.

I really don't understand the mechanism of splitting the 2 33 vector into smaller vectors. Then use multiply and addition to get the final result. Could anyone please explain how to do so.

Thank you.

Answer 1

You don't have to do that.

Just instance a 33x33 multiplier and the FPGA mapping tools will take care of splitting and recombination.

If you insist of doing it yourself look up "Wallace tree multiplier". That is the principle of how multipliers are build in hardware, with the improvement of using carry look ahead adders.