How to modify VHDL counter code and convert vector to integer correctly?

Question

We are supposed to modify a code in VHDL for counter we got from school by a line or two to count in the range from A to B. This is what we've got so far.

entity counter is
generic (
    B : integer := 4; 
    A : integer := 0
 );
port (
 CLK : IN  std_logic;
 RST : IN  std_logic;
 Q   : OUT std_logic_vector(log2(N)-1 downto 0)
);
end cntn;

architecture run01 of counter is 
signal a0 : std_logic_vector(Q'range) := (others => '0');
begin
Q <= a0;
citac: process (RST, CLK)
begin
  if RST='1' then
     a0 <= (others => std_logic_vector(conv_integer(A, cnt'length)));
  elsif rising_edge(CLK) then 
     a0 <= a0 + 1; 
       if a0 = A then 
           a0 <= (others => '0'); 
       end if;
     end if; 
  end process;
end architecture;

So far we've added this piece of code

a0 <= (others => std_logic_vector(conv_integer(A, cnt'length)));

But there seems to be problem with the conversion. Is there anyone that knows how to solve this issue? I'm pretty much new to VHDL, so I'm having a little bit hard time at this one.

Answer 1

Use ieee.numeric_std.all package. Then just write

a0 <= std_logic_vector(to_unsigned(A,a0'length));