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vhdl

Unitialized unsigned signals

Came across the following sample code:

architecture arch of disp_mux is
  constant N:integer :=18;
  signal q_reg, q_next: unsigned(N-1 downto 0);
  signal sel: std_logic_vector(1 downto 0);
begin
  process(clk, reset)
  begin
    if reset='1' then
      q_reg <= (others=>'0');
    elsif (clk'event and clk='1') then
      q_reg <= q_next;
    end if;
  end process;
  q_next <= q_reg + 1;
  sel <= std_logic_vector(q_reg(N-1 downto N-2));
  process(sel, ...)
  begin
    case sel is...
    end case;
  end process;
end arch;

If you never write 1 to reset, what is the value of q_reg? And what happens at q_next <= q_reg + 1; when/if q_reg is UUUUUUUUUUUUUUUUUU which is what I suspect it is.

Solution

  • If you never write 1 to reset, q_reg is "UUUUUUUUUUUUUUUUUU" and after executing q_next <= q_reg + 1 q_next becomes "XXXXXXXXXXXXXXXXXX".