Verilog program help 2x4 decoder

Question

I am very new to verilog and am trying to code this diagram using an an array.

2x4 Diagram

So far I have this, but I don't get the output I'm looking for.

   module DecoderMod(s, o); // module definition
   input [0:1] s;
   output [0:1] o;
   wire [0:1] snot;


   not(snot[1], s1);
   not(snot[0], s0);

   and(o[0], snot[1], snot[0]);
   and(o[1], snot[1], s[0]);
   and(o[2], s[1]   , snot[0]);
   and(o[3], s[1]   , s[0]);

endmodule

module TestMod;
   reg [0:1] s;
   wire [0:3] o;

   DecoderMod my_decoder(s, o); // create instance

   initial begin
      $monitor("%0d\t%b\t%b", $time, s, o);
      $display("Time  s  o");
      $display("--------------");
   end

   initial begin
      s[1] = 0; s[0] = 0;#1;
      s[1] = 0; s[0] = 1;#1;
      s[1] = 1; s[0] = 0;#1;
      s[1] = 1; s[0] = 1;
   end
endmodule

I get this:

Time    s       o
--------------------
0       00      x000
1       01      xx00
2       10      x0x0
3       11      xxx1

But I want this:

Time    s   o
--------------------
0       00  1000
1       01  0100
2       10  0010
3       11  0001

What am I doing wrong?

Answer 1

You are using s0 and s1 in your not instances, they should be:

 not(snot[1], s[1]);
 not(snot[0], s[0]);