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robustness of Xilinx ISE block ram inference

I have a question regarding the robustness of Xilinx ISE block ram inference.

I don't have xilinx ise installed on my machine (today) but I usually infer block rams perfectly using a dedicated coding, basically relying on :

type   ram_type is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);

My question is : could you tell me if ISE will infer a correct block ram with

signed(DATA_WIDTH-1 downto 0)` instead of `std_logic_vector(DATA_WIDTH-1 downto 0)

or even more (in a package):

subtype signed8 is signed(7 downto 0)

and then

type   ram_type is array(2**ADDR_WIDTH-1 downto 0) of signed8;

I know the synthesizers are sometimes touchy...

Solution

  • I haven't tested this myself, but the "signed" type is derived from the std_logic type, so I don't see why this shouldn't work.

    Assuming you are using XST for synthesis, the XST user guide is a good place to start to see what Xilinx officially states XST will recognize for block ram inference. XST User Guide for 12.4 (pdf)