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system-veriloguartverificationtest-bench

UART serial interface

I want to transfer 8 bits serially (1 bit/clock cycle) through a 1 bit serial interface of a UART. I created an 8 bit packet in the transaction class and drove the packet through the driver modport of the interface. Here is the code snippet below. 

        for (i = ($size(pkt.RXD)-1); i <= 0; i = i-1) begin

            RXSD_vif.DRV.cb_RXSD_DRV.RXD <= RXSD_pkt[i];

        end

RXSD_vif is the virtual interface handle.

DRV - modport

cb_RXSD_DRV is the clocking block where I'm taking the positive clock edge with RXD made out to be output.

I'm getting a compile error saying "Too many indices going into RXSD_pkt".

I'm fairly new to this and would appreciate any help in telling me how to fix this. Thanks in advance

Solution

  • I think you're passing the index 'i' to the handle of the packet class. There should be an 8 bit vector within the class through which you need to index. Does this help in any way?