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verilog

How to do explicit resize?

Is there a way to do explicit resize to LEN of an expression?

The reason I want this is to make the code explicitly describe the intention and also to avoid the warnings for implicit resize that some tools generate.

The code below works in some tools, but fails in others:

localparam EXPR = 12;
localparam LEN = 7;
assign res = LEN'(EXPR);

Based on reading the Verilog-2001 standard, it looks like length by LEN'... can only be used for literals, e.g. 7'd12, and not for general expressions.

Is there a way to do explicit resize of general expressions in Verilog-2001?

Solution

  • The syntax you are looking for is already in SystemVerilog. You need to make sure you turn it on or use the proper .sv file extension so your tools recognize it. 

    assign res = LEN'(EXPR);

    However, there is no way to dynamically calculate the length of a type - it needs to be a constant expression.

    But you can dynamically apply a mask that truncates your value to desired length

    assign res = EXPR & ((64'b10<<LEN)-1);