Configuration class for SV testbench

Question

I'm trying to write a config class for a SV testbench and wanted to decide randomization of rand fields in my transaction class, directly from the command line. I thought I could declare a static variable "mode" in my config class which takes 1 or 0 and assign this to the rand_mode (rand_mode(mode)) task called in my transaction class. Is this possible? And if so, should I declare my static variable in the config class as bit(as it needs only 1 or 0) or as boolean?

Answer 1

There is no boolean type in SystemVerilog, you can use a bit. And there is no need to make it static.

Also, consider using the UVM config db, even if your test is not written in UVM. It has built-in command line settings for configuration values.