I am creating a CPU in my VLSI, starting with a register:
library ieee;
use ieee.std_logic_1164.all;
package types is
type BYTE is array (7 downto 0) of std_logic;
end types;
-- Have to use one file because of Electric's compiler
library ieee;
use ieee.std_logic_1164.all; use work.types.all;
entity reg8 is
port (
clock : in std_logic;
inc : in std_logic;
dec : in std_logic;
store : in std_logic;
input : in BYTE;
output : out BYTE
);
end reg8;
architecture rtl of reg8 is
signal state : BYTE;
begin
tick : process(clock) is
begin
if(rising_edge(clock)) then
if inc = '1' then
state(0) <= not state(0);
state(1) <= state(0) xor state(1);
state(2) <= (state(0) and state(1)) xor state(2);
state(3) <= (state(0) and state(1) and state(2)) xor state(3);
state(4) <= (state(0) and state(1) and state(2) and state(3)) xor state(4);
state(5) <= (state(0) and state(1) and state(2) and state(3) and state(4)) xor state(5);
state(6) <= (state(0) and state(1) and state(2) and state(3) and state(4) and state(5)) xor state(6);
state(7) <= (state(0) and state(1) and state(2) and state(3) and state(4) and state(5) and state(6)) xor state(7);
elsif dec = '1' then
state(0) <= not state(0);
state(1) <= state(0) xnor state(1);
state(2) <= (state(0) or state(1)) xnor state(2);
state(3) <= (state(0) or state(1) or state(2)) xnor state(3);
state(4) <= (state(0) or state(1) or state(2) or state(3)) xnor state(4);
state(5) <= (state(0) or state(1) or state(2) or state(3) or state(4)) xnor state(5);
state(6) <= (state(0) or state(1) or state(2) or state(3) or state(4) or state(5)) xnor state(6);
state(7) <= (state(0) or state(1) or state(2) or state(3) or state(4) or state(5) or state(6)) xnor state(7);
elsif store = '1' then
state <= input;
end if;
end if;
output <= state;
end process tick;
end architecture rtl;
and I am getting weird errors that don't happen with my syntax checker, such as why I need a "PORT" keyword for a process.
Full log from Electric:
Compiling VHDL in cell 'reg8{vhdl}' ...ERROR on line 25, Expecting keyword PORT:
tick : process(clock) is
^
ERROR on line 25, Expecting keyword MAP:
tick : process(clock) is
^
ERROR on line 25, Expecting a semicolon:
tick : process(clock) is
^
ERROR on line 26, Invalid ARCHITECTURAL statement:
begin
^
ERROR on line 27, Expecting keyword END:
if(rising_edge(clock)) then
^
ERROR on line 27, Expecting a semicolon:
if(rising_edge(clock)) then
^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then
^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then
^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then
^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then
^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then
^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then
^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then
^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then
^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then
^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then
^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0);
^
ERROR on line 30, No entry keyword - entity, architectural, behavioral:
state(1) <= state(0) xor state(1);
^
TOO MANY ERRORS...PRINTING NO MORE
I am using Electric VLSI, available at http://www.staticfreesoft.com/index.html in case anyone wants to try this out.
You asked, so:
It seems this is "Electric" not a generic VHDL compiler. It only supports a certain subset and structure. I.e. what you are trying to do will probably not work. You will need to switch to a "better"(and paid) ASIC synthesis tool, like Synopsys tools.
Realizing a circuit made by an ASIC compiler using conventional transistors will likely require A LOT of transistors. And it might not even work as intended, as ASIC design programs mostly require very specific transistor properties. It would be much easier just to use a (C)PLD or some logic gate chips (7400-series) to realize your design.