Search code examples
vhdlxilinxieeeintel-fpga

Why IEEE vhdl standard library is not STL?

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator.

It seems that Altera's MAX+Plus II do not support AND2, INV component(if there are,please feel free to correct me),but Xilinx Foundation does.

Why IEEE vhdl standard library could not become something like STL in the C++ world?

thanks.

Solution

  • Invert, And, Or,... for std_logic types are supported by IEEE libraries:

    a <= b and c
d <= not e
f <= g or h

    Your synthesis tool will automatically translate these expressions to the best implementation for your target technology (Xilinx FPGA, Altera FPGA, ASIC, ...). There is no need to explicitly instantiate technology specific components. Instantiating technology specific components might even obstruct optimizations.

    You should always try to write your VHDL code technology independent. This allows you to reuse code.