assimilating values to registers in GCD FSM in verilog

Question

I'm trying to create a state machine for the GCD algorithm(subtraction method), and I need to put the values(wires) of my numbers to a register to work with the algorithm, but I don't want for each value change to assimilate into the registers.
in other words:

module GCD_R (u,v,out,nrst,act,clk);
input [31:0] A,B;
input clk,act,rst;
output reg [31:0] out;
reg[4:0] state,next_state;
reg[31:0] A_reg,B_reg,Aint_reg,Bint_reg;
parameter IDLE = 4'b0001;
parameter ABIG = 4'b0010;
parameter BBIG = 4'b0100;

always @(A,B)
    begin
        A_reg<=A
        B_reg<=B
    end
always @*   
    case (state)
        IDLE: begin

but this definition is problematic since if someone changes the values of A or B, it will move them to the registers every time and I don't want that, basically I need some condition that will move the values to the registers only on initialization, how do I do that?

Answer 1

Usually for such issues clocks are used. You even have it in parameters. So, use it:

always @(posedge clk) begin
    A_reg<=A
    B_reg<=B
end