Adding two bit_vector in VHDL return error "(vcom-1581) No feasible entries for infix operator '+'."

Question

This is my code for converting binary to BCD in VHDL

library ieee;
use ieee.numeric_bit.all;

entity bin2bcd is
    port (bin : in bit_vector(3 downto 0) := "0000";
        clk : in bit;
        bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;

architecture bin2bcdarch of bin2bcd is
begin
    process(clk)
    variable gt9 : bit;
    variable temp : bit_vector(3 downto 0) := "0110";
    variable bcdout_temp : bit_vector(4 downto 0);
    begin 
        if clk'event and clk = '1' then
            gt9 := bin(3) and(bin(2) or bin(1));
            if gt9 = '1' then
                bcdout_temp := ('0' & bin) + ('0' & temp);
            else
                bcdout_temp := ('0' & bin);
            end if;
        end if;
    bcdout <= bcdout_temp;
    end process;
end bin2bcdarch;

The problem is when i am trying to add the two bit_vector in the line

bcdout_temp := ('0' & bin) + ('0' & temp);

using "+" operator, that I get the error

(vcom-1581) No feasible entries for infix operator '+'.

Now, I looked in the web and most of the solutions are for when I use std_logic_vector.

The code works fine if I use std_logic_vector but not when I use bit_vector.

Is there any solution to the problem as to why I am getting the error?

Answer 1

You can add bit vectors if you use ieee.numeric_bit_unsigned.all which is part of VHDL-2008. The numeric_std package you're using does not define addition for bit vector.