VHDL Convert 8bit Number to hexadecimal

Question

I'm new to VHDL and i'm struggling to get input from 8 switches to create an 8 bit number which I can convert to hexadecimal to display on two 7-segment displays.

here is my current code, theirs not much so far as I'm not sure where to go from here.

ENTITY swToHex IS
    PORT ( 
        SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        HEX : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
    );
END swToHex;

ARCHITECTURE Structural OF swToHex IS
    SIGNAL A : STD_LOGIC_VECTOR(7 downto 0);
BEGIN
   A(7 downto 0) <= SW(7 downto 0);
END Structural;

Any help or resources will be appreciated as Iv only just starting learning VHDL and computer architecture.

Answer 1

You cannot directly assign a hexadecimal number to seven segment display. You need to use a decoder for this. Copy the code from, VHDL code for Hexadecimal to 7-Segment Display Converter.

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity to_7seg is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
          seg7 : out  STD_LOGIC_VECTOR (6 downto 0)
             );
end to_7seg;

architecture Behavioral of to_7seg is

begin

--'a' corresponds to MSB of seg7 and 'g' corresponds to LSB of seg7.
process (A)
BEGIN
    case A is
        when "0000"=> seg7 <="0000001";  -- '0'
        when "0001"=> seg7 <="1001111";  -- '1'
        when "0010"=> seg7 <="0010010";  -- '2'
        when "0011"=> seg7 <="0000110";  -- '3'
        when "0100"=> seg7 <="1001100";  -- '4' 
        when "0101"=> seg7 <="0100100";  -- '5'
        when "0110"=> seg7 <="0100000";  -- '6'
        when "0111"=> seg7 <="0001111";  -- '7'
        when "1000"=> seg7 <="0000000";  -- '8'
        when "1001"=> seg7 <="0000100";  -- '9'
        when "1010"=> seg7 <="0001000";  -- 'A'
        when "1011"=> seg7 <="1100000";  -- 'b'
        when "1100"=> seg7 <="0110001";  -- 'C'
        when "1101"=> seg7 <="1000010";  -- 'd'
        when "1110"=> seg7 <="0110000";  -- 'E'
        when "1111"=> seg7 <="0111000";  -- 'F'
        when others =>  NULL;
    end case;
end process;

end Behavioral;

You have two hex digits. So you will need to instantiate the to_7seg entity two times. Then connect the output of these modules to the 7 segment input ports of FPGA board.

seg1 : to_7seg port map(A(3 downto 0),HEX0);
seg2 : to_7seg port map(A(7 downto 4),HEX1);

Also HEX is not 6 bits, it should be normally 7 bits.