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vhdl

How to toggle a std_logic between 1 and 0

I want to toggle a std_logic vector '1' and '0' everytime the input sel='1'. I tried this with the following method but both lines give an error.

selected <= not selected when sel='1';

ERROR: This construct is only supported in VHDL 1076-2008

selected <= ~selected when sel='1';

ERROR: Syntax error near "~"

Is there a better way to toggle, or what is the right syntax for a 'not' function.

Here is the code for the entire architecture:

architecture Behavioral of selWeerg is

signal selected : std_logic;

begin   
process(sel,digl,sysclk)
begin
    if rising_edge(sysclk) then

        selected <= ~selected when sel='1';

        if selected = '0' then
            digO1<=digl(3 downto 0);
        else
            digO2<=digl(3 downto 0);
        end if;
    end if;
end process;
end Behavioral;
Solution

  • The error message is telling you it doesn't work: the code you are writing is only supported in VHDL-2008, not in previous versions. In previous versions, it is illegal to use the when-else construct inside a process. Why? Who knows? Which is probably why it was made legal in VHDL-2008.

    So, you either need to enable VHDL-2008 compilation on your simulator or use an if statement instead. Using VHDL-2008 is not a decision to be taken lightly, because many tools don't understand it.