Object is used but not declared

Question

I understand this is a fairly common question. Regardless, having gone through forums, I couldn't find a satisfactory answer as to why I'm getting the following CT error, for the given VHDL code. Can you help me please?

VHDL Code

library IEEE;
use IEEE.std_logic_1164.all;
entity design is
port(clk:IN std_logic;
reset:IN std_logic;
A:IN std_logic;
B:IN std_logic;
Q:OUT std_logic);
end design;

architecture behave of design is
--signal R0,R1,R2,R3,R4:std_logic;
begin
process(clk,reset)
variable R0,R1,R2,R3,R4:std_logic;
begin
if (reset='1') then
R0:='0';
R1:='0';
R2:='0';
R3:='0';
R4:='0';
elsif falling_edge(clk) then
R0:=R4;
R1:=R0 xor A;
R2:=R1 xor B;
R3:=R2;
R4:=R2 xor R3;
end if;
end process;
Q<=R4;       -- ERROR POINTED HERE
end behave;

Error:-

Error (10482): VHDL error at design.vhd(31): object "R4" is used but not declared

Is there a proper way of assigning variable to port, that I'm missing?

Answer 1

R4 is declared as a variable in the declarative region for your process. It is not visible outside of your process, so your tool is giving you the error you gave. If you move the line Q<=R4; inside your process, after the end if;, the error should go away, as the variable is still visible at this point.

With that said, I don't think your code will do what you think it will. I see that you started off using signal for R1 etc. You should probably avoid using a variable until you have a good understanding of the differences between a signal and a variable. There are other existing questions that address this.