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Simple SR Latch Simulation in VHDL(with Xilinx) doesn't oscillate

I've learned that SR-Latch does oscillate when S and R are both '0' after they were just '1' in following circuit VHDL Code.

here is VHDL of SRLATCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SRLATCH_VHDL is
port(
        S : in STD_LOGIC;
        R : in STD_LOGIC;
        Q : inout STD_LOGIC;
        NOTQ: inout STD_LOGIC);
end SRLATCH_VHDL;

architecture Behavioral of SRLATCH_VHDL is
begin

process(S,R,Q,NOTQ)
    begin
        Q <= R NOR NOTQ;
        NOTQ<= S NOR Q;
end process;

end Behavioral;

and followings are process in Testbench code and its simulation results

   -- Stimulus process
   stim_proc: process
   begin        
    S <= '1'; R <= '0'; WAIT FOR 100NS;
    S <= '0'; R <= '0'; WAIT FOR 100NS;
    S <= '0'; R <= '1'; WAIT FOR 100NS;
    S <= '0'; R <= '0'; WAIT FOR 100NS;
    S <= '1'; R <= '1'; WAIT FOR 500NS;
   end process;

and totally I don't have any idea why simulation doesn't reflect...

Xilinx Simul of SR LATCH
(click to enlarge)

Solution

  • Someone is teaching you wrong knowledge!

    SR and RS basic flip-flops (also called latches) don't oscillate. The problem on S = R = 1 (forbidden) is that you don't know the state after you leave S = R = 1 because you can never go to S = R = 0 (save) simultaneously. You will transition for S = R = 1 to S = R = 0 through S = 1; R = 0 (set) or S = 0; R = 1 (reset). This will trigger either a set or reset operation before you arrive in state save.

    Be aware that VHDL simulates with discrete time and is reproducing the same simulation results on every run. You can not (easily) simulate physical effects that cause different signal delays per simulation run.

    Btw. you VHDL description is also wrong. Q and NOTQ are of mode out, not inout. Use either a proper simulator supporting VHDL-2008 (that allows read back of out-ports) or use an intermediate signal.