I am trying to make a fsm in vhdl using modelsim but when i try and compile my code i have this errors
enter code here
entity timer_50Mhz is
generic(count : integer range 0 to 50000000 := 2);
clock_in : in STD_LOGIC;
clock_out : out STD_LOGIC);
end timer_50Mh
z;
architecture Behavioral of timer_50Mhz is
begin
process(clock_in)
variable temp :integer range 0 to 5000000 := 0;
begin
if(rising_edge(clock_in)) then
if(temp = count-1) then
temp :=0;
clock_out <='1';
else
temp := temp + 1;
clock_out <='0';
end process;
end Behavioral;
I would appreciate it if you could solve it.
This
entity timer_50Mhz is
generic(count : integer range 0 to 50000000 := 2);
clock_in : in STD_LOGIC;
clock_out : out STD_LOGIC);
end timer_50Mhz;
should be this:
entity timer_50Mhz is
generic(count : integer range 0 to 50000000 := 2);
port(
clock_in : in STD_LOGIC;
clock_out : out STD_LOGIC);
end timer_50Mhz;