In a non virtualised environment, will the “move to CR3” instruction flushes all non-global translations from all processors TLBs or is it just non-global translations from the current processors TLB, assuming we have a unified data/instruction TLB
It is only defined to flush the TLB of the current processor. However, it may also cause additional TLB entries to be flushed.
The Intel SDM says: "On a processor supporting Hyper-Threading Technology, invalidations performed on one logical processor may invalidate entries in the TLBs and paging-structure caches used by other logical processors."
It doesn't say specifically whether an invalidation on one processor can affect TLBs on other physical processors. However, I think that falls under the general guidelines: "Processors need not implement any TLBs. Processors that do implement TLBs may invalidate any TLB entry at any time. Software should not rely on the existence of TLBs or on the retention of TLB entries."
Any answer more precise than that would be implementation-specific.