i don't understand the utility of default values in state machine

Question

I am trying to understand state machine in VHDL for detecting the edge on a signal in VHDL. in next state I dont understand why we put the: "next_etat<= reg_etat" because I think it could work without any problem even without it . I'd would what are the default value of reg_etat and next_etat when we have just run the program because their is no real default value like in c for example int var=0;

entity machine_etat is
    Port ( clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        entree : in STD_LOGIC;
        tc : out STD_LOGIC);
end machine_etat;

architecture architecture_machine_etat of machine_etat is
type T_etat is (idle,edge,one);
signal next_etat, reg_etat : T_etat;
begin

registre_etat: process(clk)
begin
    if rising_edge(clk) then
        if rst = ’1’ then
            reg_etat <= idle;
        else
            reg_etat <= next_etat;
        end if;
    end if;
end process registre_etat;

tc <= ’1’ when reg_etat = edge else ’0’;

etat_suivant: process(reg_etat,entree)
begin
next_etat <= reg_etat;-- defaults values here i dont see their purpose
case reg_etat is
    when idle =>
        if entree =’1’ then
            next_etat <= edge;
        end if;
    when edge =>
        next_etat <= one;
    when one =>
        if entree =’0’ then
            next_etat <= idle;
        end if;
    end case;
end process etat_suivant;
end architecture_machine_etat;

Answer 1

If you don't assign next_etat (pardon my French) in all situations, logical synthesis will infer a latch to remember it's state. A latch is something you don't want, as it is very sensitive to digital logic latencies and might become metastable: also something you don't want.

HDL programming significantly differs from CPU programming.