should this be a multiple drive error in vhdl

Question

Consider this VHDL code:

process(a, b)
begin
    equal <= '0'; --default
    gt <= '0'; --default
    if a=b then
        equal <= '1';
    end if;
    if a>b then
        gt <= '1';
    end if;
end process;

The so called 'default' values are supposed to protect from having latches for signals gt and equal. But since this is not a clocked process shouldn't this be an error of multiple drivers for signals gt and equal?

Answer 1

This is not a multiple drive situation because your signals are driven by one single process (unless you also drive them from another process, of course). So it is fine. What puzzles you, maybe, is when the same signal is assigned several times during the same process execution. The complete and detailed answer is far too complex for this short answer. But to make it simple, if you use only simple signal assignments (no after clause, no waveforms...), then the last assignment wins.

The reason is that each time the gt <= <value> instruction is executed, the <value> is not assigned immediately to signal gt. Instead it is recorded somewhere in the simulator's memory as the value to assign to signal gt at the end of the current simulation step. And at the end of the current simulation step, after all processes have been executed and are suspended on a wait statement (or on their sensitivity list, which is equivalent to a wait statement) the simulator updates signal gt with the recorded value.

So, if you execute, in the same simulation step:

gt <= '0';
...
gt <= '1';

the second assignment will overwrite the value recorded by the first assignment and gt will take value '1' at the end of the simulation step.