how to delay a signal for several clock cycles in vhdl

Question

I'm trying to delay a signal for five clock cycles..

 process (read_clk)
begin
if (rising_edge(read_clk)) then
    rd_delay <= rd_en;
end if;
end process;

delay3 <= not(rd_en) and rd_delay;

By edge detecting technique,this will give me a one clock cycle delay, but i need five clock cycles.

Thank you all.

Answer 1

Your signal delay3 is not a delayed version of the signal rd_en, it is a pulse that is '1' for one clock cycle following a falling edge on the signal rd_en.

If you simple want to delay rd_en for five clock cycles, then add 5 flip-flops:

process (read_clk)
begin
  if rising_edge(read_clk) then
    rd_en_d5 <= rd_en_d4;
    rd_en_d4 <= rd_en_d3;
    rd_en_d3 <= rd_en_d2;
    rd_en_d2 <= rd_en_d1;
    rd_en_d1 <= rd_en;
  end if;
end process;

(Or if you have the VHDL knowledge do something a bit more elegant with an array and perhaps a for loop.)

If you then want to detect a falling edge as well, then go ahead and use something similar to the process in your question.