In Quartus 16.0, I have a foo.vhd and bar.vhd files, each containing a valid/working entity and corresponding architecture. I am trying to create a package with foo and bar in it. I have something like this:
library ieee;
use ieee.std_logic_1164.all;
package my_package is
component foo
port(
a, b : in std_logic;
out : out std_logic);
end component;
component bar
port(
a, b : in std_logic;
out : out std_logic);
end component;
end package my_package;
Trying to compile it, I receive the error: Error (12007): Top-level design entity "my_package" is undefined. I am not sure where the problem is and as a beginner don't yet know how to go about debugging it.
You are actually using a package as the top level of your design. Those two things are different. A package stores useful constants, functions, etc... whereas the top level (which is an entity) instantiates and map components between each other. Take a look at this link to see how to implement a top level entity :
https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/v_hier.html
In VHDL you don't need to add your entity (or component) in a package. You just need to compile them in the same library - usually WORK.
When compiling your top level entity, which instantiate all the components your design need, Quartus looks for the vhdl file containing the entity called by the instantiation.