SV assertion based on event trigger

Question

Assume SV interface contains a concurrent assertion property. Is it possible to enable this assertion only when an event is triggered? I tried writing property inside a task in interface file, but I ended up with error: near "property": syntax error, unexpected property.

Interface intf;

   task e1();
        -> e1; 
   endtask

   wait(e1.triggered); // something like this, where property waits for trigger 
   property prop1;
     @(posedge clk) a ##1 b;
   endproperty

endinterface

Thank you.

Answer 1

I think you need to consider that properties are best written synchronously and are evaluated on every clock cycle. You property says that one cycle after every clock cycle where a occurs b occurs. I guess what you're after is something like:

if e1 occurs, then a should be true (on the next rising edge of clk?) and then b should be true on the rising edge of clk after that

So, one way of doing that would be to create an always block that generates a pulse one clock wide should e1 occur, eg:

always begin
  @(e1);
  @(posedge clk) e = 1'b1;
  @(posedge clk) e = 1'b0;
end

property prop1;
 @(posedge clk) e |-> a ##1 b;
endproperty

or some variation of that. I feel like I should be worried about races, however.