Yosys logic loop falsely detected

Question

I've been testing yosys for some use cases. Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os)

I wrote a simple block which converts gray code to binary:

module gray2bin (gray, bin);

parameter WDT = 3;

input [WDT-1:0] gray;
output [WDT-1:0] bin;

assign bin = {gray[WDT-1], bin[WDT-1:1]^gray[WDT-2:0]};

endmodule

This is an acceptable and valid code in verilog, and there is no loop in it. It passes compilation and synthesis without any warnings in other tools. But, when I run in yosys the next commands:

read_verilog gray2bin.v
scc

I get that a logic loop was found:

Found an SCC: $xor$gray2bin.v:11$1
Found 1 SCCs in module gray2bin.
Found 1 SCCs.

The next code, which is equivalent, pass the check:

module gray2bin2 (
    gray,
    bin
);

parameter WDT = 3;

input [WDT-1:0] gray;
output [WDT-1:0] bin;

assign bin[WDT-1] = gray[WDT-1];

genvar i;
generate
    for (i = WDT-2; i>=0; i=i-1) begin : gen_serial_xor
            assign bin[i] = bin[i+1]^gray[i];
    end
endgenerate

endmodule

Am I missing a flag or synthesis option of some kind?

Answer 1

Using word-wide operators this circuit clearly has a loop (generated with yosys -p 'prep; show' gray2bin.v):

You have to synthesize the circuit to a gate-level representation to get a loop-free version (generated with yosys -p 'synth; splitnets -ports; show' gray2bin.v, the call to splitnets is just there for better visualization):