Assuming I have a system with a TrustZone enabled CPU and off-SoC DRAM that can be protected with a TZASC (e.g. TZC-400). How is access to the TZASC registers that are used to configure the access permissions for the DRAM regions controlled?
If I configure the permissions during boot up but do not lock them down because I might want to change them during run-time, can every code running in secure mode reconfigure the TZASC or is only the code running in privileged secure mode(monitor code, secure OS kernel) able to do that?
TZASC register access is also 'on the bus'. Typical ARM TrustZone solutions have two type of access control. One for memory devices and another for device mapped memory. The TZASC register set is a device. So, the access control to it will be through the 'device mapped memory' control. For example on Freescale/NXP iMx product this is controlled by the CSU.
Locking the TZASC during secure boot insures that the mapping can not change. If you need a dynamic mapping then you have the flexiblity to use whatever the device memory control support. This is different for every ARM Soc.
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