Coverpoint bins to cover all the bits

Question

I'm just a beginner in SystemVerilog and now I'm reading about coverage. So I have a doubt regarding this. How can I write the coverpoint bins to cover all the bits of a signal?

    interface allSignals;
        logic [31:0] addr;
        logic [15:0] len;
        bit trigger;

    covegroup signalOne@trigger;

        coverpoint addr; //This generates bins automatically(64 bins by 
                          default) with each bin containing 2^32/64 values

        coverpoint addr[0]; //each coverpoint covers 2 bins and 50% coverage 
        coverpoint addr[1]; //is shown even if the value is not covered in 
               ...          //that bin
               ...
        coverpoint addr[31];

        coverpoint addr{
            bins a0[] = {[0:5000]};     //should write 2^32 values which is 
            bins a1[] = {[5001:10000]}; //very complex
               ...
               ...
            }

        ad: coverpoint addr{
                bins a[100] = ad; //creates 100 bins with 2^32/100 values in 
                }                  //each bin

    endgroup

        signalOne cvr1 = new;

    endinterface

How can I write a coverpoint which covers all the 32-bits of "addr" signal. Is there any other better way to do this.

Answer 1

You are not going to collect functional coverage of a 32-bit address by trying to access 2**32 addresses. In real hardware with a 70ns access memory, it would take 5 minutes. Given that software simulation is typically 10000 times slower, that would take you a month.

What most people do is look for transitions on each bit from 0 to 1 and 1 to 0. That is toggle coverage. Although it is possible to model toggle coverage with a covergroup, most tools have built-in analysis capabilities to do this for you. You will need to check the user manual of your simulation tool.

If you really do need to exhaustively test the entire 4GB address space, you might need to investigate formal tools for that task instead of simulation.