Frequently, on a 32-bit CPU, each page-table entry is 4 bytes long, but that size can vary as well. A 32-bit entry can point to one of 2^32 physical page frames. If frame size is 4 KB (2^12), then a system with 4-byte entries can address 2^44 bytes (or 16 TB) of physical memory. We should note here that the size of physical memory in a paged memory system is different from the maximum logical size of a process.
How does paging make logical memory space more than physical memory space? Isn't total number of frames in 32-bit CPU equal to 2^(32-12)=2^20 number of frames rather than 2^32 number of frames? If so, isn't a system with 4-byte entry capable of addressing (2^20)*(2^12) bytes of memory?
That text isn't very clear admittedly. I'll try to clear it out.
When translating a virtual address into a physical one, a fixed number of lower bits don't get translated:
+---------------------+----------+
| High bits | Low bits |
+---------------------+----------+
| |
| |
V |
[Page tables] |
| |
| |
V V
+---------------------+----------+
| Physical address |
+---------------------+----------+
The lower bits number is tied to the page size: if we assume 4KiB pages then the lower 12 bits are fixed and not translated.
We also assume that the virtual address space is 32 bits.
If a page table entry is 32-bit long it can give 32 bits to use as the high part of the physical address.
Thus we have 20 (32 - 12) bits in input and 32 bits in output when looking up the page tables.
With the additional 12 bits from the fixed part this gives 32 + 12 = 44 bits of physical address.
An updated figure:
<---------- 32 bits ----------->
<---- 20 bit -------> <- 12 b ->
+---------------------+----------+
| High bits | Low bits |
+---------------------+----------+
| |
| 20 bit |
V |
[Page tables] |
| |
| 32 bit |
V V
+----------------------------+----------+
| Physical address |
+----------------------------+----------+
<-------- 32 bits ---------> <- 12 b ->
<------------- 44 bits --------------->
This is not a true 44-bit addressing however, pointers are still 32-bit.
Application can only access 4GiB of memory directly, but the OS can map an
application to the first 4GiB, another to the second 4GiB and so on.
This is similar to how PAE works on x86.
The assumption that all of a page table entry is used to give the higher bits of the physical address is untrue.
Some of the bits are used to set the attribute of the frame: cache-ability, access right, mapping status and so on.
The higher bits of the physical address are called page frames.
The number of page frames is determined by the structure of a page table entry, not by the size of the virtual address space (nor of the physical address space).
If a page table entry has 50-bit for the frame number then there are 250 frames.
The lower part of the physical address is called page offset and it is determined by the page size (or frame size, they are equal by design).