This is a question about memory organization which I have had very difficulty to understand,
Assume we have an N-way set associative cache with the capacity 4096bytes. The
set field size of the address is 7 bits and the tag field 21 bits. If we assume that
the cache is used together with a 32-bit processor, what is then the block size (in
bytes), how many valid bits does the cache contain, and what is the associativity of
the cache?
Here are some equation that is good to know in order to solve question of these type.
Parameter to know
C = cache capacity
b = block size
B = number of blocks
N = degree of associativity
S = number of set
tag_bits
set_bits (also called index)
byte_offset
v = valid bits
Equations to know
B = C/b
S = B/N
b = 2^(byte_offset)
S = 2^(set_bits)
Memory Address
|___tag________|____set___|___byte offset_|
Now to the question
known:
C = 4096 bytes
set_bits = 7
tag_bits = 21
32 bits address field
Asked:
b?
N?
v?
Simply subtract the tag_bits and set_bits from the 32 bit field this gives you the byte_offset.
byte_offset = 32-21-7 = 4 bits
b = 2^4 = 16 bytes
S = 2^7 = 128 set
B = C/b = 4096/16 = 256
N = B/S = 256/128 = 2
v = B = 256 valid bits