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scalachiselregister-transfer-level

Scopes in Chisel and scala


I am new to chisel and I have designed basic circuits and a simple risc-v processor with it but I still can't figure out how the scope works in Scala/ Chisel. Considering the following simple counter:

package example

import chisel3._

class GenericCounter(n: Int) extends Module {
  val io = IO(new Bundle {
    val ld   = Input(UInt(1.W))
    val cld  = Input(UInt(log2Ceil(n).W))
    val cout = Output(UInt(log2Ceil(n).W))
  })

  val cnt = RegInit(0.asUInt(n.W))

  when(io.ld === 1.U){
    cnt := io.cld
  } .otherwise{
    cnt :=  Mux(cnt===100.U, 0.U, cnt + 1.U)
  }
  io.cout := cnt
}

While trying to compile the above code, the compiler give an error that log2ceil is not defined. But if I use util.log2ceil it works fine. This is true for all util functions such as Cat, isPow2 etc. I know that the import chisel3._ should have imported all the necessary functions but it seems that I am missing something here. Can someone help me out?


Solution

  • In Scala, importing all of the contents of a package does not import the contents of any subpackages. Thus if you wish to import the contents of chisel.util you should also write import chisel3.util._