top level naming in chisel3

Question

class generator(options: Map[String, Any]) {
  trait for_module extends abstractModule {
    //generates trait with params
  }
  class my_module extends abstractModule with for_module
  def exec = {
    ...
    Driver.execute(Array("-tn", "SomeName", "-td", "SomePath"), () => new my_module)
    ...

  }
}
object generator {
  def main(args: Array[String]) = {
    ...
    val a = generator(someopts)
    a.exec
  }
}

In this code flag -tn should change name of top-level circuit, but it changes only top-level filename. Top module names like "module generatormy_module", but i wants to generate name dynamically from params.

Is dat bug? Or how i can change a top-level module name?

PS: suggestName method doesn't works too!

Answer 1

The flag -tn is not intended to change the top-level circuit, only to specify it and use it as a default in filenames. The way to specify the name of a Chisel module is to override the desiredName method. You can override it with an argument to the Module constructor to make it more programmable. Modifying the above example:

class generator(options: Map[String, Any]) {
  trait for_module extends abstractModule {
    //generates trait with params
  }
  class my_module(name: String) extends abstractModule with for_module {
    override def desiredName = name
  }
  def exec = {
    val topName = "SomeName"
    Driver.execute(Array("-tn", topName, "-td", "SomePath"), () => new my_module(topName))
    ...

  }
}
object generator {
  def main(args: Array[String]) = {
    ...
    val a = generator(someopts)
    a.exec
  }
}