VHDL: error when using "With Select When" Statement

Question

I'm learning VHDL using Altera Max V and Quartus to do some examples and I have a trouble when using "With Select when" statement. I have a simple 2-4 decoder as followed:

library ieee;
use ieee.std_logic_1164.all;

entity lesson9 is
    port(
        x: in std_logic_vector(1 downto 0);
        en: in std_logic;
        y: out std_logic_vector(3 downto 0)
    );
end lesson9;

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    decoder2to4: process(x)
    begin
        with x select
            outputBuff <= "0001" when "00",
                          "0010" when "01",
                          "0100" when "10",
                          "1000" when "11";
    end process decoder2to4;

    y <= outputBuff;
end rtl;

And I got the error message:

near text "with"; expecting "end", or "(", or an identifer ("with" is a reserved keyword), pr a sequential statement

I tried to check my code but couldn't find the problem ?

Answer 1

The with ... select statement is a concurrent signal assignment statement used outside of a process:

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    with x select
        outputBuff <= "0001" when "00",
                      "0010" when "01",
                      "0100" when "10",
                      "1000" when "11";

    y <= outputBuff when en='1' else (others=>'0');
end rtl;

I have also added the en signal in the output assignment statement.

Note: I did not simulate that code snippet.