modelsim verilog vsim-3365 too many port

Question

    // Dataflow description of a 4-bit comparator  
    module FourBcompare ( 
      output        A_lt_B, A_eq_B, A_gt_B, 
      input [3: 0]  A, B
    );
      assign A_lt_B = (A < B);
      assign A_gt_B = (A > B);
      assign A_eq_B = (A == B);
    endmodule

//'timescale 1 ps / 1 ps
module t_fourBcompare;

  reg   [7: 0]AB;
  wire  t_A_lt_B;
  wire  t_A_eq_B;
  wire  t_A_gt_B;
  parameter stop_time = 100;

  FourBcompare M1 (   t_A_lt_B, t_A_eq_B, t_A_gt_B ,
              AB[7],AB[6],AB[5],AB[4],
              AB[3],AB[2],AB[1],AB[0]
           );

  initial # stop_time $finish;
  initial begin                 // Stimulus generator
        AB = 8'b00000000;
    repeat (256)
   #10 AB = AB +1'b1;
  end

I can compile, but I can not simulate on modelsim.

Here is the error message:

# Compile of FourBcompare.v was successful.
# Compile of t_fourBcompare.v was successful.
# 2 compiles, 0 failed with no errors.
vsim work.t_fourBcompare
# vsim work.t_fourBcompare 
# Start time: 01:43:58 on May 02,2017
# Loading work.t_fourBcompare
# Loading work.FourBcompare
# ** Fatal: (vsim-3365) D:/util/t_fourBcompare.v(10): Too many port connections. Expected 5, found 11.
#    Time: 0 ps  Iteration: 0  Instance: /t_fourBcompare/M1 File: D:/util/FourBcompare.v
# FATAL ERROR while loading design
# Error loading design
# End time: 01:43:58 on May 02,2017, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

Answer 1

The message means that the FourBcompare module has 5 signals (2 inputs + 3 outputs), but you are trying to connect 11 signals to it. The port input [3:0] A counts as one signal, not 4.

This is one way to get rid of the errors, but you must decide if it is the correct logic for your case:

  FourBcompare M1 (   t_A_lt_B, t_A_eq_B, t_A_gt_B ,
              {AB[7],AB[6],AB[5],AB[4]},
              {AB[3],AB[2],AB[1],AB[0]}
           );

I used the concatenation operator, {}, to group individual bits into a bus. Refer to the free IEEE Std 1800-2012, section 11.4.12 Concatenation operators. Now, a 4-bit value {AB[7],AB[6],AB[5],AB[4]} is connected to the 4-bit A signal.

Note: {AB[7],AB[6],AB[5],AB[4]} can be simplified as AB[7:4].