How to initialize a VHDL std_logic_vector to "0001"

Question

i want to initialize my vectors from "0001" instead of "0000" default cause i'm doing an "automatic" 4 Bit multiplier and (x * 0) isn't useful, so I want to skip the "0000" value. Here is my Entity:

ENTITY multiplier IS
PORT (
    clk, rst : IN std_logic;
    q, r : INOUT std_logic_vector (3 DOWNTO 0)  := "0001"; -- this not work
    f : OUT std_logic_vector(7 DOWNTO 0)
); 
END multiplier;

Answer 1

Use intermediate signals

library ieee;
use ieee.std_logic_1164.all;

entity multiplier IS
    port (
        clk : in std_logic;
        rst : in std_logic;
        q : out std_logic_vector(3 downto 0);
        r : out std_logic_vector(3 downto 0);
        f : out std_logic_vector(7 downto 0)
    ); 
end entity;

architecture rtl of multiplier is
    use ieee.numeric_std.all;
    signal q_temp: unsigned(3 downto 0) := "0001"; -- or signed
    signal r_temp: unsigned(3 downto 0) := "0001"; -- or signed
begin
    [...your code...]
    q <= std_logic_vector(q_temp);
    r <= std_logic_vector(r_temp);
end architecture;