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cachingarmmicrocontrollercpu-cache

Cortex A53 L1 L2 caches info

Looking into Cortex A53, I am trying to figure out what exactly are:

  1. 8-64k I-Cache w/parity

    • What is the meaning of 8-64k? Is it 8-way set associative cache with a size of 64kByte? or is just saying the size is in a range of 8~64kByte
    • What is "w/parity"?

  2. 8-64k D-Cache w/ECC

    • What is "w/ECC"?

  3. The associativity (direct map, 2-way, 4-way ...etc) and size of L1 and L2 caches are fixed for Cortex A53 or is really up to the developer to adjust while designing the microcontroller?

Solution

  • According to this spec, this is implementation specific and can support sizes between 8 and 64k. It's not the set associativity since that's only 2 for the I-cache.

    Parity means that you have parity bits added for error detection. ECC stands for Error-correction-code which is more advanced (more bits covering different subsets of the line) and can use for error correction as well as detection.