VHDL-2008 initializing ufixed gives error in modelsim

Question

I am trying to initialize a (VHDL-2008) ufixed. But the following code gives an error in Modelsim 10.5b

entity test_e is
end entity;

library ieee;

architecture test_a of test_e is
    use ieee.fixed_pkg.all;
    constant value : ufixed(3 downto 0) := "0001";
begin
end architecture;

The error message is:

Error: [file].vhd(8): Character literal '0' of type ieee.std_logic_1164.STD_ULOGIC is not visible at the place of this string literal.

I can fix it by changing the definition line into

constant value : ufixed(3 downto 0) := to_ufixed(1,3,0);

And then when I run simulation, value holds "0001"....

I cannot figure out what I am doing wrong. I've been browsing the web for an answer, but cannot find it. Does someone know what I am doing wrong?

Answer 1

Adding an extra use statement fixes it:

entity test_e is
end entity;

library ieee;

architecture test_a of test_e is
    use ieee.std_logic_1164.all;                     -- HERE !
    use ieee.fixed_pkg.all;
    constant value : ufixed(3 downto 0) := "0001";
begin
end architecture;

Is that a bug or is it correct? I think it's correct. ufixed is declared thus:

type ufixed is array (integer range <>) of std_logic;

I'm sure you'll agree that just because you've typed use ieee.fixed_pkg.all doesn't mean you get a definition of std_logic for free. Well, I think just because you've typed use ieee.fixed_pkg.all means you don't get a definition of the std_logic literals for free, either.