My understanding is that for the cortex M4, the address register for BX and BLX must have bit(0) set to 1. I am confused how this works with regards to the BLX instruction, does the address inserted into the LR register after execution BLX instruction have bit(0) set to 1? Do I need to manually change it to 1 prior to executing a return using the BX instruction?
The other option is to use: MOV PC, LR but it seems like that is defeating the purpose of the branch instructions.
does the address inserted into the LR register after execution BLX instruction have bit(0) set to 1?
Yes.
The BLX instruction sets bit(0) of LR to 0 if the CPU was running in ARM mode before the jump and to 1 if the CPU was running in Thumb mode.
Because the Cortex M4 only supports the Thumb instruction mode (and not the ARM mode) bit(0) will always be set to 1 by BLX.
The other option is to use: MOV PC, LR but it seems like that is defeating the purpose of the branch instructions.
On the old ARM CPUs that did not have Thumb mode the MOV PC,LR instruction was the "official" return instruction.
The disadvantage is that you cannot return to a Thumb function from an ARM function and vice versa.
On a CPU that does only support Thumb mode you may also use that instruction.