vhdl simulation does not work

Question

I was writing VHDL code in order to find the numbers in a set ranging from 0 to 7 which do not have any common divisors with the other numbers in the set. I tried to implement it on BASYS 3 board. It is working on BASYS 3 but when I tried to write a test bench for my code, I got lots of U's and UU's.Why do you think this is the case? How can I write a proper test bench? I'm a beginner so any idea would help.

TOP MODULE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Top is
    Port ( Basys_Clock_Top : in STD_LOGIC;
           New_Clock_Top : out std_logic_vector(3 downto 0);
           SegDisp_Top : out std_logic_vector(6 downto 0);
           Binary_Top : out std_logic_vector(3 downto 0);
           F : out STD_LOGIC);
end Top;

architecture Behavioral of Top is
    --clock component 
    component NewClock
        Port ( New_Clock : out std_logic_vector(3 downto 0);
               Basys_Clock : in STD_LOGIC);
    end component;

    --ssd component
    component SSD
    Port ( Basys_Clock : in STD_LOGIC;
               Binary : in std_logic_vector(3 downto 0);
               SegDisplay : out std_logic_vector(6 downto 0));
    end component; 

    --signals
    signal X, Y, Z, Cont : std_logic;
    signal BCD_Top : std_logic_vector(3 downto 0);

begin
    --port maps
    NewClockModule : NewClock port map( New_Clock => New_Clock_Top, Basys_Clock => Basys_Clock_Top);
    SSDModule : SSD port map( Basys_Clock => Basys_Clock_Top, Binary => BCD_Top, SegDisplay => SegDisp_Top);

    --input assignment
    New_Clock_Top(0) <= Z;
    New_Clock_Top(1) <= Y;
    New_Clock_Top(2) <= X;

    Binary_Top <= "1110";
    F <= Z or ((not X) and Y);
    F <= Cont;

    process(BCD_Top, Cont)
    begin
        if(Cont = '1') then
            BCD_Top(0) <= Z;
            BCD_Top(1) <= Y;
            BCD_Top(2) <= X;
            BCD_Top(3) <= '0';
        else
            BCD_Top <= "1111";
        end if;
    end process;
end Behavioral; 

This is the test bench:

TEST BENCH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TestBench is
--  Port ( );
end TestBench;

architecture Behavioral of TestBench is
    component Top
        Port ( Basys_Clock_Top : in STD_LOGIC;
               New_Clock_Top : out std_logic_vector(3 downto 0);
               SegDisp_Top : out std_logic_vector(6 downto 0);
               Binary_Top : out std_logic_vector(3 downto 0);
               F : out STD_LOGIC);
    end component;

    --signals
    signal Basys_Clock_Top : STD_LOGIC;
    signal New_Clock_Top : std_logic_vector(3 downto 0);
    signal Binary_Top : std_logic_vector(3 downto 0);
    signal SegDisp_Top : std_logic_vector(6 downto 0);
    signal F : std_logic; 

begin
    uut : Top Port Map ( Basys_Clock_Top => Basys_Clock_Top, New_Clock_Top => New_Clock_Top, SegDisp_Top => SegDisp_Top, Binary_Top => Binary_Top, F => F);

    stim_proc : process
    begin
        Basys_Clock_Top <= '0';
        wait for 10 ps;
        Basys_Clock_Top <= '1';
        wait for 10 ps;
        Basys_Clock_Top <= '0';
    end process;
end Behavioral;

Answer 1

One thing I notice: in your TOP module, X, Y, Z, and Cont are not assigned anything. But you use their values....which will therefore be U