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verilogwaittest-bench

In Verilog, how to wait for level-sensitive and edge-sensitive events simultaneously?

When writing a testbench in Verilog, in a "task" I need to wait for such an event to occur, that is: while signal_a is 1'b1, signal_b is having a posedge. However, unfortunately I tried but got no good solution:

@(tb_hready and posedge tb_hclk)        ;//(1)
wait(tb_hready) @(posedge tb_hclk)      ;//(2)
wait(tb_hready && posedge tb_hclk)      ;//(3)
if(tb_hready) @(posedge tb_hclk)        ;//(4)

(1) is grammar error;

(2) grammar is good, but it will first wait for tb_hready to go high, then pick up the posedge even if tb_hready is low again; -- this is not what I want.

(3) is grammar error;

(4) grammar is good, but does NOT implement what I want, seems like in such expression it does NOT "wait" for tb_hready to become high at all.

I figured this should be something rather easy, but I just cannot get what I want, nor does Google help much. Anyone have any suggestions? thx~~

Solution 
  • @(posedge tb_hclk iff tb_hready)