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verilogmodelsim

What kind of assignment is this?


I have this verilog code from my university course which implements a basic multiplier.

//this is a portion of the code.
reg [16:0] multiplicand_copy;
input [7:0] multiplicand;

multiplicand_copy = {9'd0, multiplicand}; // this line is my question

somewhere in the code there is this assignment using brackets that i can't understand.What kind of assignment is this and what's happening in this line ?I appreciate any help.


Solution

  • reg [16:0] multiplicand_copy; 
    input [7:0] multiplicand; 
    multiplicand_copy = {9'd0, multiplicand};
    

    In this code snippet, multiplicand is 8 bits variable and multiplicand_copy is 17 bits variable.

    multiplicand_copy = {9'd0, multiplicand}; will do concatenation of 9 zeros and 8 bits of multiplicand and make assignment of 17 bits of multiplicand_copy.