Race condition between signals

Question

I've encountered a test bench which can essentially be boiled down to the below example: clock and signals are changed in the in the same timestep with blocking assignments. I believe this causes a race condition between the clock and the two ctrlX signals, but I was unable to prove in the EDA playground (I understand it's beyond my control). Am I correct that there is a race condition? (EDA Playground link: https://www.edaplayground.com/x/5yDX#&togetherjs=gkG5xewfNN)

module tb_example;


  reg clk = 1;
  reg [3:0] dff1,dff2;
  reg [3:0] ctrl1 = 'd0;
  reg [3:0] ctrl2 = 'd0;

  initial begin
    #10 ctrl1 = 'd1;
    #20 ctrl1 = 'd2;
    #10 ctrl1 = 'd3;
    #100 $finish;
  end

  always begin
    #5 clk = !clk;  
  end

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0,tb_example);
  end

  initial begin
    #10 ctrl2 = 'd1;
    #20 ctrl2 = 'd2;
    #10 ctrl2 = 'd3;
    #100 $finish;
  end

  always @ (posedge(clk)) begin
    dff1 <= ctrl1;
  end

  always @ (posedge(clk)) begin
    dff2 <= ctrl2;
  end

endmodule

Answer 1

Yes, this is a race condition because you are using blocking assignments for ctrlx and they are changing at the same time as posedge clk. So, the values assigned to dffx are indeterminate and can vary from simulator to simulator.

One way to avoid this is to change ctrlx on the negedge of clk:

  reg clk = 0;