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verilogdelayassignbidirectionalinout

How to add delay to Tri-state Buffer

I'm new to verilog, thus I have very simple question. I want to add delay before data_in assign to pad in following statement

assign pad = (enable) ? data_in : 1'bz;

something like 

assign pad = (enable) ? #10 data_in : 1'bz;

but it won't work. What's the correct way to do that?

Solution

  • You should put the delay before between assign and pad

    assign #10 pad = (enable) ? data_in : 1'bz;

    This delay will effect will be seen on the data_in and the switching to high-Z.
    You can control the rise, fail, and turn-off time separately. For example:

    assign #(10,10,0) pad = (enable) ? data_in : 1'bz;

    There is no turn-on time, so if you only want the delay on data_in, you will need to create an intermittent assignment

    wire #10 data_in_delayed = data_in;
assign pad = (enable) ? data_in_delayed : 1'bz;

    You can learn more about assign statements with delay in IEEE Std 1800-2012 § 10.3 Continuous assignments. Note SystemVerilog allows assign statements on net and variable types, Verilog only support net types.

    Also, be aware that # delays are ignored by synthesis. # delay is only for simulation.