VHDL signal assignment

Question

Assume having this code and the diagram I attached..

entity t_trigger is
     port (Test, Reset, clk, en : in std_logic;
     Q_out: out std_logic);
end t_trigger;

architecture beh_t_trigger of t_trigger is
signal temp: std_logic ;

begin
 process (Reset, clk)
 begin
 if (clk'event and clk='1') then
  if Reset='1' then
   temp <= '0';
  elsif en = '1' then
   temp <= Test xor temp;
  end if;
 end if;
end process;
Q_out <= temp;
end beh_t_trigger;

what is the state of Q_out at the end of the sequence? If the first condition is true then we skip the second? What is the initial value of temp? I cant understand what we assign to it since at first none of the "if" conditions is true..

Answer 1

I have created the following image, looks horrible but would hopefully explain the whole process for the answer;

There are 5 clock rising edges to which your logic reacts, and except the first one, you have Reset value 0, therefore first you get the Q_out value as 0, rest is always the result of temp xor Test signal for Q_out, the line I drew there represents the xor operation between those values, however ugly, I hope this was useful :)

The initial value of temp is U, as explained here, and up until you get a rising clock edge, you shouldn't worry about its value anyway, the initial out signals of your entity would probably be 0 if it were on a hardware, but on simulation you can assume it only as U, if you are worried about the out signal before the clock event, you can assign some initial value to it, but will be overwritten after first clock edge obviously.